X6-250M
Eight 310 MSPS 14-bit ADC & Virtex-6 FPGA

The X6-250M integrates digitizing with signal processing on a PMC/XMC IO module. The module has a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. Applications include software-defined radio, RADAR receivers, and multi-channel data recorders.

The X6-250M has eight simultaneously sampling A/D channels that sample at rates up to 250 MSPS (14-bit). The A/D have matched input delays and response. The A/D are supported by a programmable sample clock PLL and triggering that support multi-card synchronization for large scale systems.

Description

    Features:

  • Eight 310 MSPS, 14-bit A/D channels
  • 1.32Vp-p, AC-Coupled, 50 ohm, SSMC inputs
  • Xilinx Virtex6 SX315T/SX475T or LX240T
  •  4 Banks of 1GB DRAM (4 GB total)
  • Ultra-low jitter programmable clock
  • Gen2 x8 PCI Express option providing 2 GB/s sustained transfer rates
  • PCI 32-bit, 66 MHz with P4 to Host card PMC/XMC Module (75×150 mm) 18-22W typical Conduction Cooling per VITA 20
  • Ruggedization Levels for Wide Temperature Operation
  • Adapters for VPX, Compact PCI, desktop PCI and cabled PCI Express systems

    Applications:

  • Wireless Receiver
  • WLAN, WCDMA, WiMAX front end
  • RADAR
  • Medical Imaging
  • High Speed Data Recording and Playback
  • IP Development
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  • Download Datasheet PDF

A Xilinx Virtex6 SX315T (LX240T and SX475T options) with 4 banks of 1GB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates.

The X6-250M has both XMC and PCI interfaces, supporting PCI Express or older PCI systems. The PCI Express interface provides up to 2 GB/s sustained transfers rates through a x8 PCIe Gen2 interface.

System expansion is supported using secondary PCI Express or Aurora port used as a private data channel or second system bus.

The X6-250M power consumption is 18W for typical operation. The module may be conduction cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation from -40 to 85C operation and 0.1 g2/Hz vibration. Conformal coating is available.

The FPGA logic can be fully customized using VHDL and Matlab and the Frame Work Logic tool set. The Matlab BSP supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator. IP cores for many wireless and DSP functions such as DDC, PSK/FSK demod, OFDM receiver, correlators and large FFT are available.

Software tools for host development include C libraries and drivers for Windows, Linux and VxWorks. Application examples demonstrating the module features are provided.

Description of Change

The originally used 250MSPS ADC (LTC2157-14) was replaced with 310MSPS (LTC2158-14) part. The new part’s performance is comparable or better in the same ADC sampling rate range. Additionally, the board can now operate at up to 310 MSPS sampling rate (contact Innovative Integration if sampling rates above 250 MSPS is desirable).

The only change to X6-250M original specifications is the Input Range FS

The original specification for Input Range was 1.5 Vp-p.

The present specification for Input Range is 1.32 Vp-p.

Block Diagram

X6-250M Block Diagram

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